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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA 14-Stage Binary Ripple Counter with Oscillator High-Performance Silicon-Gate CMOS The MC54/74HC4060 is identical in pinout to the standard CMOS MC14060B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of 14 master-slave flip-flops and an oscillator with a frequency that is controlled either by a crystal or by an RC circuit connected externally. The output of each flip-flop feeds the next, and the frequency at each output is half that of the preceding one. The state of the counter advances on the negative-going edge of Osc In. The active-high Reset is asynchronous and disables the oscillator to allow very low power consumption during standby operation. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may need to be gated with Osc Out 2 of the HC4060. * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 390 FETs or 97.5 Equivalent Gates MC54/74HC4060 J SUFFIX CERAMIC PACKAGE CASE 620-10 1 16 16 1 N SUFFIX PLASTIC PACKAGE CASE 648-08 16 1 DT SUFFIX TSSOP PACKAGE CASE 948F-01 ORDERING INFORMATION MC54HCXXXXJ MC74HCXXXXN MC74HCXXXXDT Ceramic Plastic TSSOP PIN ASSIGNMENT Q12 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q10 Q8 Q9 RESET OSC IN OSC OUT 1 OSC OUT 2 LOGIC DIAGRAM OSC OUT 1 10 OSC OUT 2 9 7 5 OSC IN 11 4 6 14 13 15 1 2 3 12 PIN 16 = VCC PIN 8 = GND Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q12 Q13 Q14 X Clock Q13 Q14 Q6 Q5 Q7 Q4 GND FUNCTION TABLE Reset L L H Output State No Change Advance to Next State All Outputs are Low RESET 10/95 (c) Motorola, Inc. 1995 1 REV 6 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I III I I I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII I I III I I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* MOTOROLA DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) RECOMMENDED OPERATING CONDITIONS MC54/74HC4060 Symbol VCC = 2.0 V 0 1000 ns VCC = 4.5 V 0 500 VCC = 6.0 V 0 400 ** The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested at 2.0 V by driving Pin 11 with an external clock source. Vin, Vout Symbol Symbol VCC Vout Tstg ICC Iout VCC Vin PD TL VOH tr, tf Iin VOL TA VIH VIL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or TSSOP Package) (Ceramic DIP) Storage Temperature Power Dissipation in Still Air, Plastic or Ceramic DIP TSSOP Package DC Supply Current, VCC and GND Pins DC Output Current, per Pin DC Input Current, per Pin DC Output Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Supply Voltage (Referenced to GND) Input Rise and Fall Time (Figure 1) Operating Temperature, All Package Types DC Input Voltage, Output Voltage (Referenced to GND) DC Supply Voltage (Referenced to GND) Maximum Low-Level Output Voltage (Q4-Q10, Q12-Q14) Minimum High-Level Output Voltage (Q4-Q10, Q12-Q14) Maximum Low-Level Input Voltage Minimum High-Level Input Voltage Parameter Parameter Parameter Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| |Iout| Vin = VIH or VIL |Iout| |Iout| Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A v v v v Test Conditions - 0.5 to VCC + 0.5 - 1.5 to VCC + 1.5 - 65 to + 150 - 0.5 to + 7.0 2 2.5** - 55 Min Value v 4.0 mA v 5.2 mA v 4.0 mA v 5.2 mA 0 50 25 20 260 300 750 450 + 125 VCC Max 6.0 VCC V 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Unit Unit mW mA mA mA _C _C _C V V V V V - 55 to 25_C 1.5 3.15 4.2 0.26 0.26 3.98 5.48 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Guaranteed Limit v 85_C v 125_C High-Speed CMOS Logic Data DL129 -- Rev 6 1.5 3.15 4.2 0.33 0.33 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2 v 1.5 3.15 42 0.40 0.40 3.70 5.20 1.9 4.4 5.9 0.3 0.9 1.2 0.1 0.1 0.1 v Unit V V V V IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I NOTE: Information on typical parametric values can be found in Chapter 4. High-Speed CMOS Logic Data DL129 -- Rev 6 Symbol Symbol VOH tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL VOL tPHL fmax CPD ICC Cin Iin Maximum Quiescent Supply Current (per Package) Maximum Input Leakage Current Maximum Low-Level Output Voltage (Osc Out 1, Osc Out 2) Minimum High-Level Output Voltage (Osc Out 1, Osc Out 2) Power Dissipation Capacitance (Per Package)* Maximum Input Capacitance Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Propagation Delay, QN to QN + 1 (Figures 3 and 4) Maximum Propagation Delay, Reset to Any Q (Figures 2 and 4) Maximum Propagation Delay, Osc In to Q14* (Figures 1 and 4) Maximum Propagation Delay, Osc In to Q4* (Figures 1 and 4) Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Parameter Parameter Vin = VCC or GND Iout = 0 A Vin = VCC or GND Vin = VCC or GND IIoutI 20 A Vin = VCC or GND IIoutI 20 A * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). * For TA = 25_C and CL = 50 pF, typical propagation delay from Osc In to other Q outputs may be calculated with the following equations: VCC = 2.0 V: tP = [205 + 107.5(N - 1)] ns VCC = 4.5 V: tP = [41 + 21.5(N - 1)] ns VCC = 6.0 V: tP = [35 + 18.3(N - 1)] ns AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) (Continued) Vin = VCC or GND IIoutI IIoutI Vin = VCC or GND IIoutI IIoutI v v Test Conditions 3 v 1.0 mA v 1.3 mA v 1.0 mA v 1.3 mA VCC V VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 6.0 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 -- - 55 to 25_C - 55 to 25_C Typical @ 25C, VCC = 5.0 V 1600 320 272 0.1 0.26 0.26 3.98 5.48 125 25 21 240 48 41 530 106 91 5.0 25 29 0.1 0.1 0.1 1.9 4.4 5.9 10 75 15 13 8 Guaranteed Limit Guaranteed Limit v 85_C v 125_C v 85_C v 125_C 2000 400 344 1.0 0.33 0.33 3.84 5.34 155 31 26 300 60 51 665 133 114 4.0 20 24 0.1 0.1 0.1 1.9 4.4 5.9 10 95 19 16 80 35 MC54/74HC4060 2400 480 408 1.0 0.40 0.40 3.70 5.20 190 38 32 360 72 61 795 159 135 160 110 22 19 3.4 17 20 0.1 0.1 0.1 1.9 4.4 5.9 10 MOTOROLA MHz Unit Unit A A pF pF ns ns ns ns ns V V MC54/74HC4060 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I TIMING REQUIREMENTS (Input tr = tf = 6 ns) Guaranteed Limit Symbol trec Parameter VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - 55 to 25_C 100 20 17 80 16 14 80 16 14 v 85_C v 125_C 125 25 21 100 20 17 100 20 17 150 30 26 120 24 20 120 24 20 Unit ns Minimum Recovery Time, Reset Inactive to Osc In* (Figure 2) Minimum Pulse Width, Osc In (Figure 1) Minimum Pulse Width, Reset (Figure 2) tw ns tw ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 1000 500 400 1000 500 400 1000 500 400 ns NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). * Osc In driven with external clock. PIN DESCRIPTIONS INPUTS Osc In (Pin 11) Negative-edge triggering clock input. A high-to-low transition on this input advances the state of the counter. Osc In may be driven by an external clock source. Reset (Pin 12) Active-high reset. A high level applied to this input asynchronously resets the counter to its zero state (forcing all Q outputs low) and disables the oscillator. OUTPUTS Q4 - Q10, Q12 - Q14 (Pins 7, 5, 4, 6, 14, 13, 15, 1, 2, 3) Active-high outputs. Each QN output divides the oscillator frequency by 2N. The user should note that Q1, Q2, Q3, and Q11 are not available as outputs. Osc Out 1, Osc Out 2 (Pins 10, 9) Oscillator outputs. These pins are used in conjunction with Osc In and the external components to form an oscillator. (See Figures 4 and 5). When Osc In is being driven with an external clock source, Osc Out 1 and Osc Out 2 must be left open circuited. With the crystal oscillator configuration in Figure 6, Osc Out 2 must be left open circuited. SWITCHING WAVEFORMS tf 90% 50% 10% tw 1/fmax tPLH Q1 90% 50% 10% tTLH tTHL CLOCK tPHL Q tr VCC GND tPHL 50% trec VCC 50% GND RESET 50% GND tw VCC OSC IN Figure 2. TEST POINT OUTPUT VCC Figure 1. QN 50% tPLH QN + 1 50% tPHL GND DEVICE UNDER TEST CL* * Includes all probe and jig capacitance Figure 3. Figure 4. Test Circuit MOTOROLA 4 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC4060 EXPANDED LOGIC DIAGRAM Q4 7 Q5 5 Q12 1 Q13 2 Q14 3 C Q C Q C Q C Q C Q C Q C R 9 Q C R Q C R Q C R Q C R Q C R OSC OUT 2 OSC OUT 1 10 Q6 = PIN 4 Q7 = PIN 6 Q8 = PIN 14 Q9 = PIN 13 Q10 = PIN 15 VCC = PIN 16 GND = PIN 8 OSC IN RESET 12 11 RESET 12 For 2.0 V VCC 6.0 V 10 Rtc > RS > 2 Rtc 400 Hz f 400 kHz f 1 (f in Hz, Rtc in ohms, Ctc in farads) 3 RtcCtc OSC IN 11 OSC OUT 1 10 Rtc RS Ctc OSC OUT 2 9 The formula may vary for other frequencies. Figure 5. Oscillator Circuit Using RC Configuration High-Speed CMOS Logic Data DL129 -- Rev 6 5 MOTOROLA MC54/74HC4060 RESET 12 11 OSC IN Rf R1 C1 C2 10 OSC OUT 1 9 OSC OUT 2 Figure 6. Pierce Crystal Oscillator Circuit 1 Rs jXLs -jXCs Zload -jXCo NOTE: C = C1 + Cin and R = R1 + Rout. Co is considered as part of the load. Ca and Rf typically have minimal effect below 2 MHz. Figure 8. Series Equivalent Crystal Load MOTOROLA IIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIII I Table 1. Crystal Oscillator Amplifier Specifications TA = 25_C (Input = Pin 11, Output = Pin 10) Type Input Resistance, Rin Output Impedance, Zout (4.5 V supply) Input Capacitance, Cin Output Capacitance, Cout Series Capacitance, Ca 3 Vdc supply Open loop voltage 4 Vdc supply gain with output at 5 Vdc supply full swing, 6 Vdc supply Positive Reactance (Pierce) 60 M minimum 200 (see text) 5 pF typical 7 pF typical 5 pF typical 5.0 expected minimum 4.0 expected minimum 3.3 expected minimum 3.1 expected minimum PIERCE CRYSTAL OSCILLATOR DESIGN RS 2 1 LS CO CS 2 1 Re Xe 2 Values are supplied by crystal manufacturer (parallel resonant crystal) Figure 7. Equivalent Crystal Networks -jXC2 R Rload Ca -jXC Xload Cin Cout Values are listed in Table 1. Figure 9. Parasitic Capacitances of the Amplifier 6 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC4060 DESIGN PROCEDURES The following procedure applies for oscillators operating below 2 MHz where Z is a resistor R1. Above 2 MHz, additional impedance elements should be considered: Cout and Ca of the amp, feedback resistor Rf, and amplifier phase shift error from 180_. Step 1: Calculate the equivalent series circuit of the crystal at the frequency of oscillation. - jXCo (Rs + jXLs - jXCs Ze = = Re + jXe - jXCo + Rs + jXLs - jXCs Reactance jXe should be positive, indicating that the crystal is operating as an inductive reactance at the oscillation frequency The maximum Rs for the crystal should be used in the equation. Step 2: Determine , the attenuation, of the feedback network. For a closed-loop gain of 2, A = 2, = 2/A where A is the gain of the HC4060 amplifier. Step 3: Determine the manufacturer's loading capacitance. For example: A manufacturer may specify an external load capacitance of 32 pF at the required frequency. Step 4: Determine the required Q of the system, and calculate Rload. For example, a manufacturer specifies a crystal Q of 100,000. In-circuit Q is arbitrarily set at 20% below crystal Q or 80,000. Then Rload = (2foLs/Q) - Rs where Ls and Rs are crystal parameters. Step 5: Simultaneously solve, using a computer, = XC * XC2 (with feedback phase shift = 180_) R * Re + XC2 (Xe - XC) ReXC2 = X Cload (where the loading capacitor is an external load, not including Co) R (1) Xe = XC2 + XC + (2) Rload = RXCoXC2[(XC + XC2) (XC + XCo) - XC(XC + XCo + XC2)] X2C2(XC + XCo)2 + R2(XC + XCo + XC2)2 (3) Here R = Rout + R1. Rout is amp output resistance, R1 is Z. The C corresponding to XC is given by C = C1 + Cin. Alternately, pick a value for R1 (i.e., let R1 = Rs). Solve Equations 1 and 2 for C1 and C2. Use Equation 3 and the fact that Q = 2foLs/(Rs + Rload) to find in-circuit Q. If Q is not satisfactory pick another value for R1 and repeat the procedure. CHOOSING R1 Power is dissipated in the effective series resistance of the crystal. The drive level specified by the crystal manufacturer is the maximum stress that a crystal can withstand without damage or excessive shift in frequency R1 limits the drive level. To verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency as a function of voltage at Osc Out 2 (Pin 9). The frequency should increase very slightly as the dc supply voltage is increased. An overdriven crystal will decrease in frequency or become unstable with an increase in supply voltage. The operating supply voltage must be reduced or R1 must be increased in value it the overdriven condition exists. The user should note that the oscillator start-up time is proportional to the value of R1. SELECTING Rf The feedback resistor, Rf, typically ranges up to 20 M. Rf determines the gain and bandwidth of the amplifier. Proper bandwidth insures oscillation at the correct frequency plus roll-off to minimize gain at undesirable frequencies, such as the first overtone. Rf must be large enough so as to not affect the phase of the feedback network in an appreciable manner. ACKNOWLEDGEMENTS AND RECOMMENDED REFERENCES The following publications were used in preparing this data sheet and are hereby acknowledged and recommended for reading: Technical Note TN-24, Statek Corp. Technical Note TN-7, Statek Corp. D. Babin, "Designing Crystal Oscillators", Machine Design, March 7, 1985. D. Babin, "Guidelines for Crystal Oscillator Design", Machine Design, April 25, 1985. ALSO RECOMMENDED FOR READING: E. Hafner, "The Piezoelectric Crystal Unit - Definitions and Method of Measurement", Proc. IEEE, Vol. 57, No. 2, Feb. 1969. D. Kemper, L. Rosine, "Quartz Crystals for Frequency Control", Electro-Technology, June, 1969. P. J. Ottowitz, "A Guide to Crystal Selection", Electronic Design, May, 1966. High-Speed CMOS Logic Data DL129 -- Rev 6 7 MOTOROLA MC54/74HC4060 TIMING DIAGRAM 1 OSC IN RESET Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16,384 MOTOROLA 8 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC4060 OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 620-10 ISSUE V -A - 16 9 1 8 -B - C L NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.240 0.295 -- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15 0 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 -- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15 0 1.01 0.51 -T SEATING - PLANE N E F G D 16 PL 0.25 (0.010) M K M J 16 PL 0.25 (0.010) M TB S TA S DIM A B C D E F G J K L M N N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R -A - 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01 B 1 8 F S C L -T - H G D 16 PL 0.25 (0.010) M SEATING PLANE K J TA M M High-Speed CMOS Logic Data DL129 -- Rev 6 9 MOTOROLA MC54/74HC4060 OUTLINE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K K1 2X L/2 16 9 J1 B -U- L PIN 1 IDENT. 1 8 SECTION N-N J N 0.25 (0.010) 0.15 (0.006) T U S A -V- N F DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ M DIM A B C D F G H J J1 K K1 L M C 0.10 (0.004) -T- SEATING PLANE H D G DETAIL E Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA CODELINE 10 *MC54/74HC4060/D* EE CC EE CC EE CC EE CC -W- MC54/74HC4060/D High-Speed CMOS Logic Data DL129 -- Rev 6 |
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